diff --git a/src/cpu.rs b/src/cpu.rs
index 7891565..dd3c8c8 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -2137,7 +2137,7 @@ impl Cpu {
         };
 
         match m {
-            0 | 1 | 2 | 3 => {
+            0..=3 => {
                 // Positive Literal
                 self.set_operand(
                     index,
@@ -3039,7 +3039,7 @@ mod tests {
             {
                 cpu.set_pc(BASE as u32);
                 cpu.decode_instruction(bus).unwrap();
-                let expected_operands = vec![
+                let expected_operands = [
                     Operand::new(2, AddrMode::Register, Data::Byte, Some(Data::SByte), Some(0), 0),
                     Operand::new(
                         3,
@@ -3057,7 +3057,7 @@ mod tests {
             {
                 cpu.set_pc((BASE + 6) as u32);
                 cpu.decode_instruction(bus).unwrap();
-                let expected_operands = vec![
+                let expected_operands = [
                     Operand::new(
                         2,
                         AddrMode::ByteDisplacementDeferred,
diff --git a/src/dmd.rs b/src/dmd.rs
index 8acf5fb..9576473 100644
--- a/src/dmd.rs
+++ b/src/dmd.rs
@@ -307,7 +307,7 @@ fn dmd_mouse_up(button: u8) -> c_int {
 fn dmd_rs232_rx(c: u8) -> c_int {
     match DMD.lock() {
         Ok(mut dmd) => {
-            dmd.rs232_rx(c as u8);
+            dmd.rs232_rx(c);
             SUCCESS
         }
         Err(_) => ERROR,
diff --git a/src/duart.rs b/src/duart.rs
index f80fa28..873d5a7 100644
--- a/src/duart.rs
+++ b/src/duart.rs
@@ -512,7 +512,7 @@ impl Duart {
     }
 
     fn handle_command(&mut self, cmd: u8, port_no: usize) {
-        let mut port = &mut self.ports[port_no];
+        let port = &mut self.ports[port_no];
 
         let (tx_ists, rx_ists, dbk_ists) = match port_no {
             PORT_0 => (ISTS_TAI, ISTS_RAI, ISTS_DBA),
@@ -636,7 +636,7 @@ impl Device for Duart {
     fn read_byte(&mut self, address: usize, _access: AccessCode) -> Result<u8, BusError> {
         match (address - START_ADDR) as u8 {
             MR12A => {
-                let mut ctx = &mut self.ports[PORT_0];
+                let ctx = &mut self.ports[PORT_0];
                 let val = ctx.mode[ctx.mode_ptr];
                 ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
                 trace!("READ : MR12A, val={:02x}", val);
@@ -673,7 +673,7 @@ impl Device for Duart {
                 Ok(val)
             }
             MR12B => {
-                let mut ctx = &mut self.ports[PORT_1];
+                let ctx = &mut self.ports[PORT_1];
                 let val = ctx.mode[ctx.mode_ptr];
                 ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
                 trace!("READ : MR12B, val={:02x}", val);
@@ -722,13 +722,13 @@ impl Device for Duart {
         match (address - START_ADDR) as u8 {
             MR12A => {
                 trace!("WRITE: MR12A, val={:02x}", val);
-                let mut ctx = &mut self.ports[PORT_0];
+                let ctx = &mut self.ports[PORT_0];
                 ctx.mode[ctx.mode_ptr] = val;
                 ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
             }
             CSRA => {
                 trace!("WRITE: CSRA, val={:02x}", val);
-                let mut ctx = &mut self.ports[PORT_0];
+                let ctx = &mut self.ports[PORT_0];
                 ctx.char_delay = delay_rate(val, self.acr);
             }
             CRA => {
@@ -736,7 +736,7 @@ impl Device for Duart {
                 self.handle_command(val, PORT_0);
             }
             THRA => {
-                let mut ctx = &mut self.ports[PORT_0];
+                let ctx = &mut self.ports[PORT_0];
                 debug!("WRITE: THRA, val={:02x}", val);
                 ctx.tx_holding_reg = Some(val);
                 // TxRDY and TxEMT are both de-asserted on load.
@@ -754,13 +754,13 @@ impl Device for Duart {
             }
             MR12B => {
                 trace!("WRITE: MR12B, val={:02x}", val);
-                let mut ctx = &mut self.ports[PORT_1];
+                let ctx = &mut self.ports[PORT_1];
                 ctx.mode[ctx.mode_ptr] = val;
                 ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
             }
             CSRB => {
                 trace!("WRITE: CSRB, val={:02x}", val);
-                let mut ctx = &mut self.ports[PORT_1];
+                let ctx = &mut self.ports[PORT_1];
                 ctx.char_delay = delay_rate(val, self.acr);
             }
             CRB => {
@@ -771,7 +771,7 @@ impl Device for Duart {
                 debug!("WRITE: THRB, val={:02x}", val);
                 // TODO: When OP3 is low, do not send data to
                 // the keyboard! It's meant for the printer.
-                let mut ctx = &mut self.ports[PORT_1];
+                let ctx = &mut self.ports[PORT_1];
                 ctx.tx_holding_reg = Some(val);
                 // TxRDY and TxEMT are both de-asserted on load.
                 ctx.stat &= !(STS_TXR | STS_TXE);