More complete execution trace support
This change adds more complete and more accurate execution tracing support.
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#+TITLE: DMD 5620 Core Notes
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#+AUTHOR: Seth Morabito
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#+EMAIL: web@loomcom.com
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#+DATE: <2021-04-23 Fri 12:33>
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#+STARTUP: showall inlineimages
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#+OPTIONS: toc:nil num:nil
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* About
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This document contains miscellaneous development notes taken while working
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on devleopment.
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* Features
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** CPU Idle Loop Detection
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There are several interesting blocks that look like idle
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loops. Ideally, we want to detect these loops and just idle the CPU
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until the next interrupt is likely to occur.
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*** Idle Loop Example 1
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This tight loop occurs early on before startup is complete, and only exits
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via interrupt which sets some value in ~*$0x71a79c~.
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#+BEGIN_EXAMPLE
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[0000678d] MOVH *$0x71a79c,%r0
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[00006795] CMPW %r1,%r0
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[00006798] BLB
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#+END_EXAMPLE
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*** Idle Loop Example 2
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This occurs later on after startup is complete. It continuously calls
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the function at ~0x715c~.
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#+BEGIN_EXAMPLE
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[0000068c] BITW %r0,$0x16
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[0000068f] BEB
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[00000659] TSTB 0x6293186
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[0000065f] BNEB
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[00000661] TSTW 64(%r9)
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[00000664] BNEB
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[0000715c] CALL (%r12),0x29020
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[0000715c] SAVE %r9
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[0000715e] MOVW $0x71c590,%r1
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[00007161] ADDW3 $0x71c590,0x1096,%r0
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[00007169] TSTH (%r0)
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[0000716b] BLEB
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[00007170] MOVW *$0x719024,%r0
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[00007177] MOVW (%r0),%r0
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[0000717a] TSTH 52(%r0)
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[0000717d] BLEB
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[00007182] MOVW %r1,%r0
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[00007185] RESTORE %r9
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[0000068c] RET
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#+END_EXAMPLE
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13
src/bus.rs
13
src/bus.rs
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@ -5,8 +5,8 @@ use crate::err::BusError;
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use crate::mem::Mem;
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use crate::mouse::Mouse;
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use std::io::Write;
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use std::{fmt, fs::File, ops::Range};
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use std::{fmt::Debug, fs::OpenOptions};
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use std::{fs::File, ops::Range};
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const NVRAM_SIZE: usize = 8192;
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@ -108,8 +108,8 @@ impl Bus {
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}
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pub fn trace_on(&mut self, name: &str) -> std::io::Result<()> {
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let mut out = OpenOptions::new().write(true).open(name)?;
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write!(out, "TRACE START")?;
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let mut out = OpenOptions::new().create(true).write(true).open(name)?;
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writeln!(out, "TRACE START")?;
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self.trace_log = Some(out);
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Ok(())
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}
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@ -122,12 +122,9 @@ impl Bus {
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self.trace_log = None;
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}
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pub fn trace<T>(&mut self, step: u64, object: &T)
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where
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T: fmt::Display,
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{
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pub fn trace(&mut self, step: u64, line: &str) {
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if let Some(trace_log) = &mut self.trace_log {
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let _ = writeln!(trace_log, "{:08}: {}", step, object);
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let _ = writeln!(trace_log, "{:08}: {}", step, line);
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}
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}
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136
src/cpu.rs
136
src/cpu.rs
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@ -48,6 +48,14 @@ const IPL_TABLE: [u32; 64] = [
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const WE32100_VERSION: u32 = 0x1a;
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const HALFWORD_MNEMONIC_COUNT: usize = 11;
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macro_rules! trace {
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($bus:ident, $steps:expr, $msg:expr) => {
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if ($bus.trace_enabled()) {
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$bus.trace($steps, $msg)
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}
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};
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}
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pub enum ExceptionType {
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ExternalMemory,
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}
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@ -152,6 +160,15 @@ impl Operand {
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None => self.data_type,
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}
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}
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fn clear(&mut self) {
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self.size = 0;
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self.mode = AddrMode::None;
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self.data_type = Data::None;
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self.expanded_type = None;
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self.register = None;
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self.embedded = 0;
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}
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}
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#[derive(Clone, Debug, Eq, PartialEq)]
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@ -173,16 +190,59 @@ pub struct Instruction {
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impl fmt::Display for Operand {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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match self.data_type {
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Data::None => Ok(()),
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Data::Byte | Data::SByte => {
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write!(f, "0x{:02x}", self.data as u8)
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match self.mode {
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AddrMode::None => Ok(()),
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AddrMode::Absolute => {
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write!(f, "0x{}", self.data)
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}
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Data::Half | Data::UHalf => {
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write!(f, "0x{:04x}", self.data as u16)
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AddrMode::AbsoluteDeferred => write!(f, "*$0x{:x}", self.data),
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AddrMode::ByteDisplacement => {
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write!(f, "{}(%r{})", self.data as i8, self.register.unwrap())
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}
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Data::Word | Data::UWord => {
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write!(f, "0x{:08x}", self.data)
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AddrMode::ByteDisplacementDeferred => {
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write!(f, "*{}(%r{})", self.data as i8, self.register.unwrap())
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}
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AddrMode::HalfwordDisplacement => {
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write!(f, "0x{:x}(%r{})", self.data as i16, self.register.unwrap())
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}
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AddrMode::HalfwordDisplacementDeferred => {
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write!(f, "*0x{:x}(%r{})", self.data as i16, self.register.unwrap())
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}
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AddrMode::WordDisplacement => {
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write!(f, "0x{:x}(%r{})", self.data, self.register.unwrap())
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}
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AddrMode::WordDisplacementDeferred => {
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write!(f, "*0x{:x}(%r{})", self.data, self.register.unwrap())
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}
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AddrMode::ApShortOffset => {
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write!(f, "{}(%ap)", self.data as i8)
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}
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AddrMode::FpShortOffset => {
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write!(f, "{}(%fp)", self.data as i8)
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}
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AddrMode::ByteImmediate => {
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write!(f, "&{}", self.data as u8)
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}
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AddrMode::HalfwordImmediate => {
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write!(f, "&0x{:x}", self.data as u16)
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}
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AddrMode::WordImmediate => {
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write!(f, "&0x{:x}", self.data)
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}
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AddrMode::PositiveLiteral => {
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write!(f, "$0x{:x}", self.data)
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}
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AddrMode::NegativeLiteral => {
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write!(f, "-$0x{:x}", self.data)
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}
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AddrMode::Register => {
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write!(f, "%r{}", self.register.unwrap())
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}
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AddrMode::RegisterDeferred => {
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write!(f, "(%r{})", self.register.unwrap())
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}
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AddrMode::Expanded => {
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write!(f, "{{???}}")
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}
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}
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}
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@ -190,11 +250,23 @@ impl fmt::Display for Operand {
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impl fmt::Display for Instruction {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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write!(
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f,
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"{:5} {}{}{}{}",
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self.name, self.operands[0], self.operands[1], self.operands[2], self.operands[3]
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)
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let _ = write!(f, "{:8} ", self.name);
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for index in 0..=3 {
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let op = &self.operands[index];
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if op.mode == AddrMode::None {
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break;
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}
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if index == 0 {
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let _ = write!(f, "{}", op);
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} else {
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let _ = write!(f, ",{}", op);
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}
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}
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Ok(())
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}
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}
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@ -948,6 +1020,11 @@ impl Cpu {
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if let Some(val) = bus.get_interrupts() {
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let cpu_ipl = (self.r[R_PSW]) >> 13 & 0xf;
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if cpu_ipl < IPL_TABLE[(val & 0x3f) as usize] {
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trace!(
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bus,
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self.steps,
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&format!("[{:08x}] INTERRUPT 0x{:x}", &self.r[R_PC], (!val) & 0x3f)
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);
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self.on_interrupt(bus, (!val) & 0x3f);
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}
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}
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@ -955,8 +1032,6 @@ impl Cpu {
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self.decode_instruction(bus)?;
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let mut pc_increment: i32 = i32::from(self.ir.bytes);
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bus.trace(self.steps, &self.ir);
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match self.ir.opcode {
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NOP => {
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pc_increment = 1;
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@ -1905,18 +1980,24 @@ impl Cpu {
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pub fn step(&mut self, bus: &mut Bus) {
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// TODO: On CPU Exception or Bus Error, handle each error with the appropriate exception handler routine
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match self.dispatch(bus) {
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Ok(i) => self.r[R_PC] = (self.r[R_PC] as i32 + i) as u32,
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Err(CpuError::Bus(BusError::Alignment)) => {}
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Err(CpuError::Bus(BusError::Permission)) => {}
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Ok(i) => {
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// We should have the necessary information to trace after dispatch.
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trace!(bus, self.steps, &format!("[{:08x}] {}", &self.r[R_PC], &self.ir));
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self.r[R_PC] = (self.r[R_PC] as i32 + i) as u32
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}
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Err(CpuError::Bus(BusError::NoDevice(_)))
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| Err(CpuError::Bus(BusError::Read(_)))
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| Err(CpuError::Bus(BusError::Write(_))) => {
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self.on_exception(bus, &ExceptionType::ExternalMemory).unwrap();
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}
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Err(CpuError::Exception(CpuException::IllegalOpcode)) => {}
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Err(CpuError::Exception(CpuException::InvalidDescriptor)) => {}
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Err(CpuError::Exception(CpuException::PrivilegedOpcode)) => {}
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Err(_) => {}
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// Err(CpuError::Bus(BusError::Alignment)) => {}
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// Err(CpuError::Bus(BusError::Permission)) => {}
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// Err(CpuError::Exception(CpuException::IllegalOpcode)) => {}
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// Err(CpuError::Exception(CpuException::InvalidDescriptor)) => {}
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// Err(CpuError::Exception(CpuException::PrivilegedOpcode)) => {}
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Err(e) => {
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panic!("Unexpected CPU Error: {}", e)
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}
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}
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}
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@ -2393,12 +2474,13 @@ impl Cpu {
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for (index, ot) in mn.ops.iter().enumerate() {
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if *ot == OpType::None {
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break;
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self.ir.operands[index].clear();
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} else {
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// Push a decoded operand
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self.decode_operand(bus, index, mn, *ot, etype, addr)?;
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etype = self.ir.operands[index].expanded_type;
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addr += self.ir.operands[index].size as usize;
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}
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// Push a decoded operand
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self.decode_operand(bus, index, mn, *ot, etype, addr)?;
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etype = self.ir.operands[index].expanded_type;
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addr += self.ir.operands[index].size as usize;
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}
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let total_bytes = addr - initial_addr;
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@ -175,8 +175,14 @@ fn dmd_step() -> c_int {
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}
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}
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/// # Safety
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///
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/// Uses a raw pointer.
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///
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#[no_mangle]
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fn dmd_trace_on(file_name: &CStr) -> c_int {
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pub unsafe fn dmd_trace_on(file_name: *const c_char) -> c_int {
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let file_name = CStr::from_ptr(file_name);
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match DMD.lock() {
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Ok(mut dmd) => match file_name.to_str() {
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Ok(file_name) => match dmd.trace_on(file_name) {
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