Fix video ram start address and DUART bugs

Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "dmd_core"
 description = "AT&T / Teletype DMD 5620 Terminal Emulator - Core Library"
-version = "0.6.2"
+version = "0.6.3"
 authors = ["Seth Morabito <web@loomcom.com>"]
 homepage = "https://github.com/sethm/dmd_core"
 repository = "https://github.com/sethm/dmd_core"

README.md

@@ -27,6 +27,10 @@ however.
 
 ## Changelog
 
+0.6.3: Bug fixes: Video Ram starting address was not being
+       updated correctly for video ram read; Implement
+       `read_word` for DUART (needed to run `gebaca`)
+
 0.6.2: Fix UART character delay timing.
 
 0.6.1: Fix failing tets.

src/bus.rs

@@ -162,7 +162,10 @@ impl Bus {
     }
 
     pub fn video_ram(&self) -> &[u8] {
-        self.ram.as_slice(0x0..0x19000)
+        let vid_register = (u16::from(self.vid[0]) << 8 | u16::from(self.vid[1])) as usize;
+        let start = vid_register * 4;
+        let end = start + 0x19000;
+        self.ram.as_slice(start..end)
     }
 
     pub fn service(&mut self) {

src/duart.rs

@@ -471,12 +471,14 @@ impl Device for Duart {
         }
     }
 
-    fn read_half(&mut self, _address: usize, _access: AccessCode) -> Result<u16, BusError> {
-        unimplemented!()
+    fn read_half(&mut self, address: usize, access: AccessCode) -> Result<u16, BusError> {
+        let b = self.read_byte(address + 2, access)?;
+        Ok(u16::from(b))
     }
 
-    fn read_word(&mut self, _address: usize, _access: AccessCode) -> Result<u32, BusError> {
-        unimplemented!()
+    fn read_word(&mut self, address: usize, access: AccessCode) -> Result<u32, BusError> {
+        let b = self.read_byte(address + 3, access)?;
+        Ok(u32::from(b))
     }
 
     fn write_byte(&mut self, address: usize, val: u8, _access: AccessCode) -> Result<(), BusError> {
@@ -558,12 +560,12 @@ impl Device for Duart {
         Ok(())
     }
 
-    fn write_half(&mut self, _address: usize, _val: u16, _access: AccessCode) -> Result<(), BusError> {
-        unimplemented!()
+    fn write_half(&mut self, address: usize, val: u16, access: AccessCode) -> Result<(), BusError> {
+        self.write_byte(address + 2, val as u8, access)
     }
 
-    fn write_word(&mut self, _address: usize, _val: u32, _access: AccessCode) -> Result<(), BusError> {
-        unimplemented!()
+    fn write_word(&mut self, address: usize, val: u32, access: AccessCode) -> Result<(), BusError> {
+        self.write_byte(address + 3, val as u8, access)
     }
 
     fn load(&mut self, _address: usize, _data: &[u8]) -> Result<(), BusError> {