parent
4131b2262c
commit
c9161324b5
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@ -1,7 +1,7 @@
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[package]
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name = "dmd_core"
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description = "AT&T / Teletype DMD 5620 Terminal Emulator - Core Library"
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version = "0.7.0"
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version = "0.6.5"
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authors = ["Seth Morabito <web@loomcom.com>"]
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homepage = "https://github.com/sethm/dmd_core"
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repository = "https://github.com/sethm/dmd_core"
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12
src/bus.rs
12
src/bus.rs
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@ -41,10 +41,6 @@ pub trait Device: Send + Sync + Debug {
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fn write_half(&mut self, address: usize, val: u16, access: AccessCode) -> Result<(), BusError>;
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fn write_word(&mut self, address: usize, val: u32, access: AccessCode) -> Result<(), BusError>;
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fn load(&mut self, address: usize, data: &[u8]) -> Result<(), BusError>;
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fn dirty(&self) -> bool {
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false
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}
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fn clear_dirty(&mut self) {}
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}
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//
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@ -171,14 +167,6 @@ impl Bus {
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self.ram.as_slice(start..end)
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}
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pub fn video_ram_dirty(&self) -> bool {
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self.vid.dirty()
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}
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pub fn video_ram_clear_dirty(&mut self) {
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self.vid.clear_dirty()
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}
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pub fn service(&mut self) {
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self.duart.service();
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}
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133
src/dmd.rs
133
src/dmd.rs
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@ -1,6 +1,6 @@
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#![allow(clippy::unreadable_literal)]
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use crate::bus::{AccessCode, Bus};
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use crate::bus::{Bus, AccessCode};
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use crate::cpu::Cpu;
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use crate::err::BusError;
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use crate::rom_hi::HI_ROM;
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@ -52,14 +52,6 @@ impl Dmd {
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self.bus.video_ram()
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}
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pub fn video_ram_dirty(&self) -> bool {
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self.bus.video_ram_dirty()
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}
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pub fn video_ram_clear_dirty(&mut self) {
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self.bus.video_ram_clear_dirty()
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}
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pub fn get_pc(&self) -> u32 {
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self.cpu.get_pc()
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}
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@ -148,34 +140,23 @@ impl Dmd {
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#[no_mangle]
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fn dmd_reset() -> c_int {
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match DMD.lock() {
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Ok(mut dmd) => match dmd.reset() {
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Ok(()) => SUCCESS,
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Err(_) => ERROR,
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},
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Err(_) => ERROR,
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Ok(mut dmd) => {
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match dmd.reset() {
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Ok(()) => SUCCESS,
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Err(_) => ERROR
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}
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}
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Err(_) => ERROR
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}
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}
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#[no_mangle]
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fn dmd_video_ram() -> *const u8 {
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match DMD.lock() {
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Ok(dmd) => dmd.video_ram().as_ptr(),
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Err(_) => ptr::null(),
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}
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}
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#[no_mangle]
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fn dmd_video_ram_dirty() -> bool {
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match DMD.lock() {
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Ok(dmd) => dmd.video_ram_dirty(),
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Err(_) => false,
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}
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}
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#[no_mangle]
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fn dmd_video_ram_clear_dirty() {
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if let Ok(mut dmd) = DMD.lock() {
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dmd.video_ram_clear_dirty();
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Ok(dmd) => {
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dmd.video_ram().as_ptr()
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}
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Err(_) => ptr::null()
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}
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}
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@ -186,7 +167,7 @@ fn dmd_step() -> c_int {
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dmd.step();
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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@ -196,8 +177,8 @@ fn dmd_step_loop(steps: usize) -> c_int {
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Ok(mut dmd) => {
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dmd.run(steps);
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SUCCESS
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}
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Err(_) => ERROR,
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},
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Err(_) => ERROR
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}
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}
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@ -207,8 +188,8 @@ fn dmd_get_pc(pc: &mut u32) -> c_int {
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Ok(dmd) => {
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*pc = dmd.get_pc();
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SUCCESS
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}
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Err(_) => ERROR,
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},
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Err(_) => ERROR
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}
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}
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@ -218,36 +199,40 @@ fn dmd_get_register(reg: u8, val: &mut u32) -> c_int {
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Ok(dmd) => {
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*val = dmd.get_register(reg);
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SUCCESS
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}
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Err(_) => ERROR,
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},
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Err(_) => ERROR
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}
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}
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#[no_mangle]
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fn dmd_read_word(addr: u32, val: &mut u32) -> c_int {
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match DMD.lock() {
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Ok(mut dmd) => match dmd.read_word(addr as usize) {
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Some(word) => {
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*val = word;
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SUCCESS
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Ok(mut dmd) => {
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match dmd.read_word(addr as usize) {
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Some(word) => {
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*val = word;
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SUCCESS
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},
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None => ERROR
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}
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None => ERROR,
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},
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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#[no_mangle]
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fn dmd_read_byte(addr: u32, val: &mut u8) -> c_int {
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match DMD.lock() {
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Ok(mut dmd) => match dmd.read_byte(addr as usize) {
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Some(byte) => {
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*val = byte;
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SUCCESS
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Ok(mut dmd) => {
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match dmd.read_byte(addr as usize) {
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Some(byte) => {
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*val = byte;
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SUCCESS
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},
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None => ERROR
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}
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None => ERROR,
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},
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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@ -258,7 +243,7 @@ fn dmd_get_duart_output_port(oport: &mut u8) -> c_int {
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*oport = dmd.duart_output();
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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@ -269,7 +254,7 @@ fn dmd_rx_char(c: u8) -> c_int {
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dmd.rx_char(c as u8);
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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@ -280,7 +265,7 @@ fn dmd_rx_keyboard(c: u8) -> c_int {
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dmd.rx_keyboard(c);
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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@ -291,7 +276,7 @@ fn dmd_mouse_move(x: u16, y: u16) -> c_int {
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dmd.mouse_move(x, y);
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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@ -302,7 +287,7 @@ fn dmd_mouse_down(button: u8) -> c_int {
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dmd.mouse_down(button);
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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@ -313,35 +298,39 @@ fn dmd_mouse_up(button: u8) -> c_int {
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dmd.mouse_up(button);
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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#[no_mangle]
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fn dmd_rs232_tx_poll(tx_char: &mut u8) -> c_int {
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match DMD.lock() {
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Ok(mut dmd) => match dmd.rs232_tx_poll() {
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Some(c) => {
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*tx_char = c;
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SUCCESS
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Ok(mut dmd) => {
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match dmd.rs232_tx_poll() {
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Some(c) => {
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*tx_char = c;
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SUCCESS
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}
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None => BUSY
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}
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None => BUSY,
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},
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Err(_) => ERROR,
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}
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Err(_) => ERROR
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}
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}
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#[no_mangle]
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fn dmd_kb_tx_poll(tx_char: &mut u8) -> c_int {
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match DMD.lock() {
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Ok(mut dmd) => match dmd.kb_tx_poll() {
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Some(c) => {
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*tx_char = c;
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SUCCESS
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Ok(mut dmd) => {
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match dmd.kb_tx_poll() {
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Some(c) => {
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*tx_char = c;
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SUCCESS
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}
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None => BUSY
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}
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None => BUSY,
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},
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Err(_) => ERROR,
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}
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Err(_) => ERROR
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}
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}
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@ -352,7 +341,7 @@ fn dmd_set_nvram(nvram: &[u8; 8192]) -> c_int {
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dmd.set_nvram(nvram);
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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@ -363,7 +352,7 @@ fn dmd_get_nvram(nvram: &mut [u8; 8192]) -> c_int {
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nvram.clone_from_slice(dmd.get_nvram());
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SUCCESS
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}
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Err(_) => ERROR,
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Err(_) => ERROR
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}
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}
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51
src/duart.rs
51
src/duart.rs
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@ -4,28 +4,34 @@ use crate::bus::AccessCode;
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use crate::bus::Device;
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use crate::err::BusError;
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use std::collections::VecDeque;
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use std::fmt::Debug;
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use std::fmt::Error;
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use std::fmt::Formatter;
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use std::ops::Range;
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use std::time::Duration;
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use std::time::Instant;
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use std::collections::VecDeque;
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const START_ADDR: usize = 0x200000;
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const END_ADDR: usize = 0x2000040;
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const ADDRESS_RANGE: Range<usize> = START_ADDR..END_ADDR;
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// Vertical blanks should occur at 60Hz. This value is in nanoseconds
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const VERTICAL_BLANK_DELAY: u32 = 16_666_666; // 60 Hz
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const VERTICAL_BLANK_DELAY: u32 = 16_666_666; // 60 Hz
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// Delay rates, in nanoseconds, selected when ACR[7] = 0
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const DELAY_RATES_A: [u32; 13] =
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[160000000, 72727272, 59259260, 40000000, 26666668, 13333334, 6666667, 7619047, 3333333, 1666666, 1111111, 833333, 208333];
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const DELAY_RATES_A: [u32;13] = [
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160000000, 72727272, 59259260, 40000000,
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26666668, 13333334, 6666667, 7619047,
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3333333, 1666666, 1111111, 833333, 208333
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];
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// Delay rates, in nanoseconds, selected when ACR[7] = 1
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const DELAY_RATES_B: [u32; 13] =
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[106666672, 72727272, 59259260, 53333336, 26666668, 13333334, 6666667, 4000000, 3333333, 1666666, 4444444, 833333, 416666];
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const DELAY_RATES_B: [u32;13] = [
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106666672, 72727272, 59259260, 53333336,
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26666668, 13333334, 6666667, 4000000,
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3333333, 1666666, 4444444, 833333, 416666
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];
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const PORT_0: usize = 0;
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const PORT_1: usize = 1;
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@ -47,6 +53,7 @@ const IP_OPCR: u8 = 0x37;
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const OPBITS_SET: u8 = 0x3b;
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const OPBITS_RESET: u8 = 0x3f;
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//
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// Port Configuration Bits
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//
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@ -89,7 +96,7 @@ const TX_INT: u8 = 0x10;
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const RX_INT: u8 = 0x20;
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struct Port {
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mode: [u8; 2],
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mode: [u8;2],
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stat: u8,
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conf: u8,
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rx_data: u8,
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@ -135,7 +142,7 @@ pub struct Duart {
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istat: u8,
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imr: u8,
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ivec: u8,
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next_vblank: Instant,
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next_vblank: Instant
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}
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impl Default for Duart {
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@ -147,7 +154,10 @@ impl Default for Duart {
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impl Duart {
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pub fn new() -> Duart {
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Duart {
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ports: [Port::new(), Port::new()],
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ports: [
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Port::new(),
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Port::new(),
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],
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acr: 0,
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ipcr: 0x40,
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inprt: 0xb,
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@ -206,7 +216,10 @@ impl Duart {
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_ => (ISTS_TBI, ISTS_RBI),
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};
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if (ctx.conf & CNF_ETX) != 0 && (ctx.stat & STS_TXR) == 0 && (ctx.stat & STS_TXE) == 0 && Instant::now() >= ctx.next_tx {
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if (ctx.conf & CNF_ETX) != 0 &&
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(ctx.stat & STS_TXR) == 0 &&
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(ctx.stat & STS_TXE) == 0 && Instant::now() >= ctx.next_tx
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{
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let c = ctx.tx_data;
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ctx.stat |= STS_TXR;
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ctx.stat |= STS_TXE;
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@ -382,7 +395,7 @@ impl Duart {
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ctx.stat |= STS_TXE;
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ctx.conf &= !CNF_ETX;
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}
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4 => ctx.stat &= !(STS_FER | STS_PER | STS_OER),
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4 => ctx.stat &= !(STS_FER|STS_PER|STS_OER),
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_ => {}
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}
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}
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@ -415,7 +428,9 @@ impl Device for Duart {
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ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
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Ok(val)
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}
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CSRA => Ok(self.ports[PORT_0].stat),
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CSRA => {
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Ok(self.ports[PORT_0].stat)
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}
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THRA => {
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let mut ctx = &mut self.ports[PORT_0];
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ctx.stat &= !STS_RXR;
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@ -430,14 +445,18 @@ impl Device for Duart {
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self.istat &= !ISTS_IPC;
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Ok(result)
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}
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ISR_MASK => Ok(self.istat),
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ISR_MASK => {
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Ok(self.istat)
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}
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MR12B => {
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let mut ctx = &mut self.ports[PORT_1];
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let val = ctx.mode[ctx.mode_ptr];
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ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
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Ok(val)
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}
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CSRB => Ok(self.ports[PORT_1].stat),
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CSRB => {
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Ok(self.ports[PORT_1].stat)
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}
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THRB => {
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let mut ctx = &mut self.ports[PORT_1];
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ctx.stat &= !STS_RXR;
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@ -445,7 +464,9 @@ impl Device for Duart {
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self.ivec &= !KEYBOARD_INT;
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Ok(ctx.rx_data)
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}
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IP_OPCR => Ok(self.inprt),
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IP_OPCR => {
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Ok(self.inprt)
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}
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_ => Ok(0),
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}
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}
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|
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|
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@ -1,14 +1,14 @@
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pub mod bus;
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pub mod cpu;
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pub mod dmd;
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pub mod duart;
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pub mod err;
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pub mod instr;
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pub mod mem;
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pub mod duart;
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pub mod mouse;
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pub mod rom_hi;
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pub mod rom_lo;
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|
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#[macro_use]
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extern crate lazy_static;
|
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extern crate libc;
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extern crate libc;
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45
src/mem.rs
45
src/mem.rs
|
|
@ -6,27 +6,25 @@ use crate::err::BusError;
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|||
use std::fmt::Debug;
|
||||
use std::fmt::Error;
|
||||
use std::fmt::Formatter;
|
||||
use std::ops::Range;
|
||||
use std::ops::{Index, IndexMut};
|
||||
use std::vec::Vec;
|
||||
use std::ops::Range;
|
||||
|
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pub struct Mem {
|
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address_range: Range<usize>,
|
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len: usize,
|
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ram: Vec<u8>,
|
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is_read_only: bool,
|
||||
dirty: bool,
|
||||
}
|
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|
||||
/// Memory is a Device with a single address range.
|
||||
impl Mem {
|
||||
pub fn new(start_address: usize, len: usize, is_read_only: bool) -> Mem {
|
||||
Mem {
|
||||
address_range: start_address..start_address + len,
|
||||
address_range: start_address..start_address+len,
|
||||
len,
|
||||
ram: vec![0; len],
|
||||
is_read_only,
|
||||
dirty: false,
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -93,7 +91,7 @@ impl Device for Mem {
|
|||
u32::from(self.ram[offset]).wrapping_shl(24)
|
||||
| u32::from(self.ram[offset + 1]).wrapping_shl(16)
|
||||
| u32::from(self.ram[offset + 2]).wrapping_shl(8)
|
||||
| u32::from(self.ram[offset + 3]),
|
||||
| u32::from(self.ram[offset + 3])
|
||||
)
|
||||
}
|
||||
}
|
||||
|
|
@ -109,9 +107,6 @@ impl Device for Mem {
|
|||
if address >= self.address_range().end {
|
||||
Err(BusError::Range)
|
||||
} else {
|
||||
if self.ram[offset] != val {
|
||||
self.dirty = true;
|
||||
}
|
||||
self.ram[offset] = val;
|
||||
Ok(())
|
||||
}
|
||||
|
|
@ -127,13 +122,8 @@ impl Device for Mem {
|
|||
if address >= self.address_range().end {
|
||||
Err(BusError::Range)
|
||||
} else {
|
||||
let b1 = (val.wrapping_shr(8) & 0xff) as u8;
|
||||
let b2 = (val & 0xff) as u8;
|
||||
if self.ram[offset] != b1 || self.ram[offset + 1] != b2 {
|
||||
self.dirty = true;
|
||||
}
|
||||
self.ram[offset] = b1;
|
||||
self.ram[offset + 1] = b2;
|
||||
self.ram[offset] = (val.wrapping_shr(8) & 0xff) as u8;
|
||||
self.ram[offset + 1] = (val & 0xff) as u8;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
|
@ -148,19 +138,10 @@ impl Device for Mem {
|
|||
if address >= self.address_range().end {
|
||||
Err(BusError::Range)
|
||||
} else {
|
||||
let b1 = (val.wrapping_shr(24) & 0xff) as u8;
|
||||
let b2 = (val.wrapping_shr(16) & 0xff) as u8;
|
||||
let b3 = (val.wrapping_shr(8) & 0xff) as u8;
|
||||
let b4 = (val & 0xff) as u8;
|
||||
|
||||
if self.ram[offset] != b1 || self.ram[offset + 1] != b2 || self.ram[offset + 2] != b3 || self.ram[offset + 3] != b4 {
|
||||
self.dirty = true;
|
||||
}
|
||||
|
||||
self.ram[offset] = b1;
|
||||
self.ram[offset + 1] = b2;
|
||||
self.ram[offset + 2] = b3;
|
||||
self.ram[offset + 3] = b4;
|
||||
self.ram[offset] = (val.wrapping_shr(24) & 0xff) as u8;
|
||||
self.ram[offset + 1] = (val.wrapping_shr(16) & 0xff) as u8;
|
||||
self.ram[offset + 2] = (val.wrapping_shr(8) & 0xff) as u8;
|
||||
self.ram[offset + 3] = (val & 0xff) as u8;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
|
@ -179,14 +160,6 @@ impl Device for Mem {
|
|||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
fn dirty(&self) -> bool {
|
||||
self.dirty
|
||||
}
|
||||
|
||||
fn clear_dirty(&mut self) {
|
||||
self.dirty = false;
|
||||
}
|
||||
}
|
||||
|
||||
impl Index<usize> for Mem {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#![allow(clippy::unreadable_literal)]
|
||||
|
||||
use crate::bus::AccessCode;
|
||||
use crate::bus::Device;
|
||||
use crate::bus::AccessCode;
|
||||
use crate::err::BusError;
|
||||
use std::ops::Range;
|
||||
|
||||
|
|
@ -48,7 +48,7 @@ impl Device for Mouse {
|
|||
}
|
||||
|
||||
fn read_half(&mut self, address: usize, _access: AccessCode) -> Result<u16, BusError> {
|
||||
match address - START_ADDRESS {
|
||||
match address-START_ADDRESS {
|
||||
0 => Ok(self.y),
|
||||
2 => Ok(self.x),
|
||||
_ => Err(BusError::NoDevice(address as u32)),
|
||||
|
|
@ -74,4 +74,4 @@ impl Device for Mouse {
|
|||
fn load(&mut self, _address: usize, _data: &[u8]) -> Result<(), BusError> {
|
||||
unimplemented!()
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue