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Clean up clippy suggestions

This commit is contained in:
Seth Morabito 2023-09-02 10:20:21 -07:00
parent d19f3d4fdb
commit 00c0cb77b1
3 changed files with 13 additions and 13 deletions
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6
src/cpu.rs
View File

@ -2137,7 +2137,7 @@ impl Cpu {
}; };
match m { match m {
0 | 1 | 2 | 3 => { 0..=3 => {
// Positive Literal // Positive Literal
self.set_operand( self.set_operand(
index, index,
@ -3039,7 +3039,7 @@ mod tests {
{ {
cpu.set_pc(BASE as u32); cpu.set_pc(BASE as u32);
cpu.decode_instruction(bus).unwrap(); cpu.decode_instruction(bus).unwrap();
let expected_operands = vec![ let expected_operands = [
Operand::new(2, AddrMode::Register, Data::Byte, Some(Data::SByte), Some(0), 0), Operand::new(2, AddrMode::Register, Data::Byte, Some(Data::SByte), Some(0), 0),
Operand::new( Operand::new(
3, 3,
@ -3057,7 +3057,7 @@ mod tests {
{ {
cpu.set_pc((BASE + 6) as u32); cpu.set_pc((BASE + 6) as u32);
cpu.decode_instruction(bus).unwrap(); cpu.decode_instruction(bus).unwrap();
let expected_operands = vec![ let expected_operands = [
Operand::new( Operand::new(
2, 2,
AddrMode::ByteDisplacementDeferred, AddrMode::ByteDisplacementDeferred,

2
src/dmd.rs
View File

@ -307,7 +307,7 @@ fn dmd_mouse_up(button: u8) -> c_int {
fn dmd_rs232_rx(c: u8) -> c_int { fn dmd_rs232_rx(c: u8) -> c_int {
match DMD.lock() { match DMD.lock() {
Ok(mut dmd) => { Ok(mut dmd) => {
dmd.rs232_rx(c as u8); dmd.rs232_rx(c);
SUCCESS SUCCESS
} }
Err(_) => ERROR, Err(_) => ERROR,

18
src/duart.rs
View File

@ -512,7 +512,7 @@ impl Duart {
} }
fn handle_command(&mut self, cmd: u8, port_no: usize) { fn handle_command(&mut self, cmd: u8, port_no: usize) {
let mut port = &mut self.ports[port_no]; let port = &mut self.ports[port_no];
let (tx_ists, rx_ists, dbk_ists) = match port_no { let (tx_ists, rx_ists, dbk_ists) = match port_no {
PORT_0 => (ISTS_TAI, ISTS_RAI, ISTS_DBA), PORT_0 => (ISTS_TAI, ISTS_RAI, ISTS_DBA),
@ -636,7 +636,7 @@ impl Device for Duart {
fn read_byte(&mut self, address: usize, _access: AccessCode) -> Result<u8, BusError> { fn read_byte(&mut self, address: usize, _access: AccessCode) -> Result<u8, BusError> {
match (address - START_ADDR) as u8 { match (address - START_ADDR) as u8 {
MR12A => { MR12A => {
let mut ctx = &mut self.ports[PORT_0]; let ctx = &mut self.ports[PORT_0];
let val = ctx.mode[ctx.mode_ptr]; let val = ctx.mode[ctx.mode_ptr];
ctx.mode_ptr = (ctx.mode_ptr + 1) % 2; ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
trace!("READ : MR12A, val={:02x}", val); trace!("READ : MR12A, val={:02x}", val);
@ -673,7 +673,7 @@ impl Device for Duart {
Ok(val) Ok(val)
} }
MR12B => { MR12B => {
let mut ctx = &mut self.ports[PORT_1]; let ctx = &mut self.ports[PORT_1];
let val = ctx.mode[ctx.mode_ptr]; let val = ctx.mode[ctx.mode_ptr];
ctx.mode_ptr = (ctx.mode_ptr + 1) % 2; ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
trace!("READ : MR12B, val={:02x}", val); trace!("READ : MR12B, val={:02x}", val);
@ -722,13 +722,13 @@ impl Device for Duart {
match (address - START_ADDR) as u8 { match (address - START_ADDR) as u8 {
MR12A => { MR12A => {
trace!("WRITE: MR12A, val={:02x}", val); trace!("WRITE: MR12A, val={:02x}", val);
let mut ctx = &mut self.ports[PORT_0]; let ctx = &mut self.ports[PORT_0];
ctx.mode[ctx.mode_ptr] = val; ctx.mode[ctx.mode_ptr] = val;
ctx.mode_ptr = (ctx.mode_ptr + 1) % 2; ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
} }
CSRA => { CSRA => {
trace!("WRITE: CSRA, val={:02x}", val); trace!("WRITE: CSRA, val={:02x}", val);
let mut ctx = &mut self.ports[PORT_0]; let ctx = &mut self.ports[PORT_0];
ctx.char_delay = delay_rate(val, self.acr); ctx.char_delay = delay_rate(val, self.acr);
} }
CRA => { CRA => {
@ -736,7 +736,7 @@ impl Device for Duart {
self.handle_command(val, PORT_0); self.handle_command(val, PORT_0);
} }
THRA => { THRA => {
let mut ctx = &mut self.ports[PORT_0]; let ctx = &mut self.ports[PORT_0];
debug!("WRITE: THRA, val={:02x}", val); debug!("WRITE: THRA, val={:02x}", val);
ctx.tx_holding_reg = Some(val); ctx.tx_holding_reg = Some(val);
// TxRDY and TxEMT are both de-asserted on load. // TxRDY and TxEMT are both de-asserted on load.
@ -754,13 +754,13 @@ impl Device for Duart {
} }
MR12B => { MR12B => {
trace!("WRITE: MR12B, val={:02x}", val); trace!("WRITE: MR12B, val={:02x}", val);
let mut ctx = &mut self.ports[PORT_1]; let ctx = &mut self.ports[PORT_1];
ctx.mode[ctx.mode_ptr] = val; ctx.mode[ctx.mode_ptr] = val;
ctx.mode_ptr = (ctx.mode_ptr + 1) % 2; ctx.mode_ptr = (ctx.mode_ptr + 1) % 2;
} }
CSRB => { CSRB => {
trace!("WRITE: CSRB, val={:02x}", val); trace!("WRITE: CSRB, val={:02x}", val);
let mut ctx = &mut self.ports[PORT_1]; let ctx = &mut self.ports[PORT_1];
ctx.char_delay = delay_rate(val, self.acr); ctx.char_delay = delay_rate(val, self.acr);
} }
CRB => { CRB => {
@ -771,7 +771,7 @@ impl Device for Duart {
debug!("WRITE: THRB, val={:02x}", val); debug!("WRITE: THRB, val={:02x}", val);
// TODO: When OP3 is low, do not send data to // TODO: When OP3 is low, do not send data to
// the keyboard! It's meant for the printer. // the keyboard! It's meant for the printer.
let mut ctx = &mut self.ports[PORT_1]; let ctx = &mut self.ports[PORT_1];
ctx.tx_holding_reg = Some(val); ctx.tx_holding_reg = Some(val);
// TxRDY and TxEMT are both de-asserted on load. // TxRDY and TxEMT are both de-asserted on load.
ctx.stat &= !(STS_TXR | STS_TXE); ctx.stat &= !(STS_TXR | STS_TXE);